2nd Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec’24)

March 25-27, 2024, Valencia, Spain co-located with Design Automation and Test in Europe (DATE) Conference

2nd Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec’24)

25 March 2024, Valencia, Spain, co-located with Design Automation and Test in Europe (DATE) Conference

Workshop at DATE'24

Workshop Scope

Today’s societies critically depend on electronic systems. Security of such systems are facing completely new challenges due to the ongoing transition to radically new types of nano-electronic devices, such as memristors, spintronics, or carbon nanotubes. The use of such emerging nano-technologies is inevitable to address the essential needs related to energy efficiency, computing power and performance. Therefore, the entire industry are switching to emerging nano-electronics alongside scaled CMOS technologies in heterogeneous integrated systems. These technologies come with new properties and also facilitate the development of radically different computer architectures.

The second edition of the NanoSec workshop will bring together researchers from hardware-oriented security and from emerging hardware technology. It will explore the potential of new technologies and architectures to provide new opportunities for achieving security targets, but it will also raise questions about their vulnerabilities to new types of hardware-oriented attacks. The workshop is based on a Priority Program https://spp-nanosecurity.uni-stuttgart.de/ funded since 2019 by the German DFG, and will be open to members and non-members of that Priority Program alike.

Technical Program

Session chair: Michael Hutter, PQShield Vienna

The Impact of Logic Synthesis and Technology Mapping on Logic Locking Security
Lilas Alrahis, NYU Abu Dhabi

Session chair: Giorgio Di Natale, TIMA, Grenoble

Okapi: A Lightweight Architecture for Secure Speculation Exploiting Locality of Memory Accesses
Philipp Schmitz1 , Tobias Jauch1 , Alex Wezel1 , Mohammad R. Fadiheh2, Thore Tiemann3 , Jonah Heller3, Thomas Eisenbarth3, Dominik Stoffel1, Wolfgang Kunz1
1RPTU Kaiserslautern-Landau, 2Stanford U, 3U Lübeck

Neuromorphic and In-Memory Computing Based on Memristive Circuits for Predictive Maintenance and Supply-Chain Management and Security
Nikolaos Athanasios Anagnostopoulos, Nico Mexis, Stefan Katzenbeisser, Elif Bilge Kavun, Tolga Arul,
U Passau

OnE-Secure: Securing State-of-the-Art Chips Against High-Resolution Contactless Optical and Electron-Beam Probing Attacks
Sebastian Brand (FhG IMWS), Rolf Drechsler (U Bremen), Jean-Pierre Seifert TU Berlin), Frank Sill Torres (DLR)

STAMPS-PLUS: Exploration of an integrated Strain-based TAMPer Sensor for Puf and trng concepts with best-in-class Leakage resilience and robUStness
Ralf Brederlow (TU Munich), Matthias Hiller (FhG AISEC), Michael Pehl (TU Munich)

RAINCOAT: Randomization in Secure Nano-Scale Microarchitectures 2
Lucas Davi (U Duisburg-Essen), Tim Güneysu (RU Bochum)

EMBOSOM: Embedded Software Security into Modern Emerging Hardware Paradigms
Rolf Drechsler (U Bremen), Tim Güneysu (RU Bochum)

MemCrypto: Towards Secure Electroforming-free Memristive Cryptographic Implementations
Nan Du (FSU Jena), Ilia Polian (U Stuttgart)

HaSPro: Verifiable Hardware Security for Out-of-Order Processors
Thomas Eisenbarth (U Lübeck), Wolfgang Kunz (TU Kaiserslautern)

NanoSec2: Nanomaterial-based platform electronics for PUF circuits with extended entropy sources
Sascha Herrmann (TU Chemnitz), Stefan Katzenbeisser (U Passau), Elif Kavun (U Passau)

SecuReFET: Secure Circuits through Inherent Reconfigurable FET
Akash Kumar (TU Dresden), Thomas Mikolajick (NaMLab GmbH)

SSIMA: Scalable Side-Channel Immune Micro-Architecture
Amir Moradi (TU Darmstadt)

SeMSiNN: Secure Mixed-SIgnal Neural Networks
Maurits Ortmanns (U Ulm), Ilia Polian (U Stuttgart)

Session Chair: Francesco Regazzoni, University of Amsterdam and ALARI, Lugano

Hardware Trojan Detection Using Optical Probing
Sajjad Parvin1, Frank Sill Torres2, Rolf Drechsler1
1U Bremen, 2DLR Bremen

A Cautionary Note about Bit Flips in ReRAM
Felix Staudigl1, Jan Philipp Thoma2, Christian Niesler3, Karl J. X. Sturm1, Rebecca Pelke1, Dominik Sisejkovic1, Jan Moritz Joseph1, Tim Güneysu2, Lucas Davi3, Rainer Leupers1
1RWTH Aachen, 2RU Bochum, 3U Duisburg Essen

An Analysis of the Effects of Temperature on the Performance of ReRAM-Based TRNGs
Nico Mexis, Nikolaos Athanasios Anagnostopoulos, Stefan Katzenbeisser, Tolga Arul, U Passau

Session chair: Haralampos Stratigopoulos, Sorbonne University, CNRS, LIP6, Paris

A Guide to Assessing Emerging Reconfigurable Nanotechnologies for Robust IP Protection
Armin Darjani, Nima Kavand, Akash Kumar, TU Dresden

Fingerprinting and Identification of Hall Sensors
Christoph Frisch1, Tobias Chlan1, Carl Riehm1, Markus Sand2, Markus Stahl-Offergeld3, Michael Pehl1, Ralf Brederlow1,3
1TU Munich, 2LZE GmbH, 3Fraunhofer Institute for Integrated Circuits IIS

Memristors in the Context of Security and AI
Alexander Tekles, Tolga Arul, Nico Mexis, Stefan Katzenbeisser, Nikolaos Athanasios Anagnostopoulos, U Passau

March 25, 2024

Call for Papers

The workshop invites submissions on, but not limited to, the following topics:

  • Nano-electronic security primitives, such as physical unclonable functions, random number generators, cryptographic blocks, reconfigurable nano-fabrics, or obfuscation/camouflaging structures
  • Integration of secure primitives into larger systems, protocols and architectures, translating security guarantees defined and validated for lower-level primitives in higher-order, system- and architecture-level security properties
  • Attacks against systems with nano-electronic components, including side-channel analysis, fault injection, microarchitectural covert channels, and countermeasures against such attacks

A submission can describe a novel scientific result, provide a position statement about a new and relevant problem, or report a case study on practical experiences with a technique from the list above. The submissions should not be formally published in the past. The workshop will have no formal proceedings, so authors will be free to resubmit their work to conferences or journals. Accepted papers can, at the discretion and with an approval of their authors, be published on the workshop’s website.

Call for Papers

Author instructions:

Submissions in form of full 6-page papers or 1-2 page extended abstracts (in IEEE double-column format, either A4 or US Letter) should be submitted through EasyChair:


Key dates:

Submission deadline: January 15, 2024
Acceptance notification: January 25, 2024

PDF file for publishing on the workshop’s website (optional): March 10, 2024

Workshop: March 25, 2024, 14:00-18:00

This workshop is co-located with the Design, Automation and Test in Europe Conference and will use its registration facilities. Please register through the DATE website. The early-bird deadline is January 24, 2024.

Date Website

Workshop organizers:

Ilia Polian, University of Stuttgart, Germany
Nan Du, Friedrich Schiller University Jena, Germany
Shahar Kvatinsky, Technion – Israel Institute of Technology
Ingrid Verbauwhede, KU Leuven, Belgium

The workshop is organized by the Priority Program Nano Security


This image shows Ilia Polian

Ilia Polian

Prof. Dr. rer. nat. habil.

University of Stuttgart

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