Projects

Description of funded and associated projects.
Further projects will be added shortly.

MemCrypto: Towards Secure Electroforming-free Memristive Cryptographic Implementations

Project title: Towards Secure Electroforming-free Memristive Cryptographic Implementations

Acronym: MemCrypto

Principal Investigators:

Project Staff: N.N.

Available open position:

Resaerch assistent at University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Hocos Department

Attribution within the Priority Program:

Area 1 "Nano-electronics for Security"

Area 2 "Hardware Security and Cryptography"

Interdisciplinary Group IG3 "Physical Attack Resilience"

Link to Project Website: https://www.iti.uni-stuttgart.de/en/institute/projects/memcrypto/

Project Abstract: Memristive devices offer enormous advantages for non-volatile memories and neuromorphic computing, but there is a rising interest in using memristive technologies for security applications. Project MemCrypto aims at development and investigation of memristive cryptographic implementations, assessment and improvement of their security against physical attacks. This work focuses on combinational and sequential realizations of complete cryptographic circuits and complements earlier research on memristive physical unclonable functions and random number generators.

Within MemCrypto, simplified cryptographic circuits will be physically built out of novel electroforming-free memristive devices fabricated as wire-bonded line arrays using pulsed laser deposition. Physical attacks (side-channel analysis and fault injections) against memristive circuits will be studied, with a focus on identifying and characterizing novel attack mechanisms that do not exist in conventional CMOS technology. For instance, side-channel analysis could utilize effects of memristance and nonvolatility, and fault injections can target both memristive devices and their control logic. Three representative memristive logic families will be explored and low-level protections for information leakage reduction will be developed for all of them, as well as the development of combination of these low-level protections with higher-level masking. We will also perform an experimental comparative study with commercially available memristive devices (with requirement of an electroforming step) and with a CMOS implementation on an FPGA.

A further objective of MemCrypto is to develop electrical simulation models and simulation procedures suitable for security analysis before physical realization of a circuit. On the one hand, we will improve the accuracy of existing Spice-level simulation models by better reflecting switching performances in endurance and retention. On the other hand, we will devise mixed-level simulation procedures that balance between accuracy and simulation speed and are meant for evaluation of physical attacks in medium-size memristive circuits. Using such procedures, we will extend the findings gathered on reduced-scale physical implementations to fully-fledged cryptographic circuits.

MemCrypto is a tandem project that will strongly benefit from interdisciplinary collaboration of both applicants. Ilia Polian will provide competencies in hardware-oriented security, design of complex electronic circuits and mixed-level simulation algorithms. Nan Du, as a co-inventor of the electroforming free BiFeO3 based memristive device family exploited in MemCrypto, will contribute her knowledge in fabrication, characterization, optimization, modeling and simulation of memristive devices. Together, the applicants are a team that includes complementary abilities to holistically address all relevant security aspects of using memristive technologies for cryptographic circuits.

NANOSEC: Tamper-Evident PUFs based on Nanostructures for Secure and Robust Hardware Security Primitives

Project title: Tamper-Evident PUFs based on Nanostructures for Secure and Robust Hardware Security Primitives

Acronym: NANOSEC

Principal Investigators:

Project Staff:

  • N.N.
  • Simon Böttger (TU Chemnitz)

Available open position:

Attribution within the Priority Program: 

  • Area 1 "Nano-electronics for Security"
  • Interdisciplinary Group IG1 "Secret Generation"

Link to Project Website: https://www.fim.uni-passau.de/en/computer-engineering/research/

Project Abstract: In recent years, pronounced trends like the Internet of Things or 5G has led to more and more connected and digitalized cyber-physical systems. This results in an increased demand on embedded dedicated hardware security. Hence, unclonable, unpredictable and tamper-evident hardware security primitives, such as Physical Unclonable Functions (PUFs), became more and more important, since any software-only security solution can easily be defeated in case an attacker has full access to the device. In this tandem-project, we will investigate the suitability of nanomaterial-based devices such as Carbon Nanotube based field-effect transistors (CNT-FETs) for hardware security primitives featuring high entropy and robustness along with inherent tamper-evidence capabilities. Going beyond state of the art, we investigate important security characteristics like error correction, reliability, and tamper-evidence mechanisms of CNT-based PUFs. These investigations will induce novel insights regarding the applicability of such PUFs for forthcoming system integration technologies and in the emerging field of flexible/wearable electronics. We will cover technological developments for CNT-based PUFs and investigate different device designs which internalize multibit functionality as well as tamper-evidence. The realized PUFs will be subjected to an in-depth analysis exposing suitable error correction models to enable the extraction of stable PUF responses.

PUFMem: Intrinsic Physical Unclonable Functions from Emerging Non-Volatile Memories

Project title: Intrinsic Physical Unclonable Functions from Emerging Non-Volatile Memories

Acronym: PUFMem

Principal Investigators:

Project Staff: N.N.

Attribution within the Priority Program:

Area 1 "Nano-electronics for Security"

Interdisciplinary Group IG1 "Secret Generation"

Link to Project Website: https://www.fim.uni-passau.de/en/computer-engineering/research/

Project Abstract: Recent developments have led to the proliferation of resource constrained devices that undertake increasingly extensive and decisive tasks. Based on physical process variations during semiconductor manufacturing, memory-based physical unclonable functions (PUFs) provide lightweight, cost-efficient, and flexible hardware-based security primitives to protect these devices. Concurrently with these trends, the integration density of circuits is approaching the so-called scaling limit, where structures become so small that the saved information are hard to retrieve and that consequently brings novel non-volatile memory (NVM) types to the scene.

In this project, we investigate the realization of intrinsic PUFs on commercially available NVMs. All obtained PUF instances will be systematically characterized according to established quality metrics. As PUFs from conventional memories are susceptible to varying temperature and supply voltage as well as magnetic fields and radiation, different environmental conditions for the characterization of PUF instances on NVMs will be created. In the next step, we will quantify the results and apply advanced techniques such as protocols, error correcting codes, stochastic models etc. to improve PUF quality and resilience to influences from the environment. In particular when used as random access memory in present-day computers, credentials and results of cryptographic operations are directly accessible on NVMs due to their inherent storage properties. We plan to overcome this drawback by employing self-encryption, where the same NVM is used for 2 different purposes: as a memory to store data and as a PUF for retrieving the key to encrypt this data.

BioNanoLock: Bio-Nanoelectronic based Logic Locking for Secure Systems

Project title: Bio-Nanoelectronic based Logic Locking for Secure Systems

Acronym: BioNanoLock

Principal Investigators:

Project Staff: N.N.

Available open position: 2 doctoral positions (TBA)

Attribution within the Priority Program:

Area 1 "Nano-electronics for Security"

Interdisciplinary Group IG2 "Secure Processing"

Link to Project Website: TBA

Project Abstract: The new age processor is going to require hardware-oriented solutions as a primary design criterion for the security against threats. Alternative computational architectures proposed in recent years drive this idea by the inclusion of multi-value logic operations. The realization of multi-value logic gates and testing the advantages of polymorphic inputs and outputs of a circuit, however, remains elusive due to the technology gap. In this project, we put forward a new logic-locking framework that will allow us incorporating multi-value and multi-layer logic with existing CMOS based logic-locking architectures. An encoded DNA sequence acts as a secret 'biological activation-key' which is molecularly recognized at a unique and secret pattern of key-gates called biological key-gates and activates them. This, in turn, enables the CMOS based key-gates in logic-locked circuit with the appropriate key value. Different voltage-levels in the multi-valued logic define "on" or "off" state of the key-gates adding another level of ambiguity for an attacker and making it impossible for the attacker to unlock the circuit. Enabling future-generation processors with BioNanoLock is the prime target of the project with small (10-100 logic gates) to medium-sized (100-10000 logic gates) circuits as an intermediate goal. We also envision developing heterogeneous integrated systems for secure information processing in the long-term.

HaSPro: Verifiable Hardware Security for Out-of-Order Processors

Project title: Verifiable Hardware Security for Out-of-Order Processors

Acronym: HaSPro

Principal Investigators:

Project Staff:

  • Mohammad Fadiheh
  • Johannes Müller
  • TBA

Attribution within the Priority Program:

Area 2 "Hardware Security and Cryptography"

Area 3 "Secure Composition and Integration"

Interdisciplinary Group IG3 "Physical Attack Resilience"

Link to Project Website: https://www.its.uni-luebeck.de/forschung/haspro.html

Project Abstract: Sicherheitslücken in Software haben in den letzten Jahren zu zunehmend schwerwiegenden Sicherheitsverletzungen geführt, nicht zuletzt aufgrund unserer Abgängigkeit von der IT Infrastruktur, die mit der Digitalisierung weiter ansteigt. Prozessorhardware wurde lange als zuverlässiger und leistungsfähiger Vertrauensanker gesehen - bis im Januar 2018 mit Spectre und Meltdown eine neue Klasse von Seitenkanalangriffen bekannt wurde. Seitdem ist Hardwaresicherheit in den Fokus der Forschung und der Allgemeinheit gerückt, wie zahlreiche Artikel in den Medien weltweit belegen.

Spectre und Meltdown gehören zur Klasse der sogenannten Transient Execution Angriffe. Diese Angriffe sind besonders gravierend für hardwareunterstützte Sicherheitsmechanismen, insbesondere für sichere Ausführungsumgebungen (TEEs) wie beispielsweise Intel SGX und ARM Trustzone. TEEs ermöglichen sichere Enklaven, die Prozesse durch hardwaregestützte Isolation schützen - insbesondere gegen privilegierte Angriffe auf Systemebene, also beispielsweise kompromittierte Betriebssysteme.

Dieses Projekt motiviert sich aus zwei Beobachtungen: (I) Sicherheitslücken in Software resultieren in zunehmend gravierenden Datenverlusten und kompromittierten Systemen, (II) ein beständiger Strom an neu gefundenen Mikroarchitekturangriffen untergräbt das Vertrauen in die bestehenden Modelle in der Hardwaresicherheit. Beide Probleme können durch eine Kombination aus verbesserter Hardware sowie besseren Hardwareentwurfsverfahren gelöst werden. Statt auf jeden einzelnen Angriff mit ad hoc Lösungen zu reagieren, verfolgt dieses Projekt das Ziel, einen systematischen Ansatz zur Detektion und zum Schutz vor diesen Angriffen bereits während des Entwurfsphase sowie auf der Hardwareebene sicherzustellen. Konkret wird (I) eine sichere Ausführungsumgebung ohne Schwachstellen Prozesse vor Sicherheitslücken im System schützen und (II) ein verifizierbar seitenkanalfreier Prozessor sicherstellen, dass die logische Trennung von Prozessen innerhalb der CPU wirklich effektiv ist und nicht von Entwurfsfehlern in der Hardware untergraben wird.

Im Rahmen dieses Projekts werden neue Techniken zur Elektronischen Entwurfsautomatisierung (EDA) entwickelt, mit denen Mikroarchitekturen entworfen werden können, die gegen spezifische Klassen von Seitenkanalangriffen geschützt sind, inklusive Transient Execution Angriffe. Aufbauend auf diesen Werkzeugen zur Verifikation der Seitenkanalresistenz erforscht das Projekt neue seitenkanalresistente TEE-Technologie, die hardwarebasierte Vertrauensanker - ein erklärtes Ziel des dieses SPPs - für die Mikroarchitektur moderner Prozessoren schafft. Mit Hilfe der entwickelten Werkzeuge und TEE werden offene RISC-V-basierten Prozessoren analysiert und sicherer gemacht.

RRAM-PUFTRNG: CMOS-compatible RRAM-based structures for the implementation of Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG)

Project title: CMOS-compatible RRAM-based structures for the implementation of Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG)

Acronym: RRAM-PUFTRNG

Principal Investigators:

Project Staff:

  • TBA

Attribution within the Priority Program:

Area 1 “Nano-electronics for Security“

Interdisciplinary Group IG1 “Secret Generation”

Link to Project Website: TBA

Project Abstract: Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two components widely used nowadays to generate random bit streams in security applications. The huge increase in the last decade in the use of portable consumer electronics has revealed the security in wireless communications as one of the most important requirements to be fulfilled in microelectronics technology. Therefore, it is of great interest to develop an implementation of these components which accomplishes the following characteristics: low-power operation, high-integration density, and compatibility with CMOS processes. Following the “More than Moore” approach (Increase of the performance adding functionality) such characteristics can be achieved. For instance, Resistive Random Access Memories (RRAM) have emerged in the last years as promising candidates in the field of Non-Volatile Memories (NVM). Moreover, the mechanisms behind switching operations in RRAM devices are intrinsically stochastic. Therefore, RRAM technology has started recently to be considered as a suitable solution to implement the future PUF and TRNG components.

The study proposed in this project involves interdisciplinary research in order to achieve three main targets:

  1. Studying in detail the statistical distributions of the electrical parameters involved in RRAM switching, which have been typically used as a source of randomness.

  2. Figuring out how the correlations which avoid the true randomness emerge from fundamental physical and chemical processes.

  3. Development of an appropriate operative algorithm able to overcome the correlations found on the electrical parameters of RRAM devices providing the true random digital outputs required for both TRNG and PUF applications.

In order to understand why the electrical characteristics of RRAM devices are intrinsically stochastic but not true random, a complete materials study and electrical characterization will be performed with these devices. The RRAM-based structures required for this characterization will be fabricated by starting from the well-known TiN/HfO2/Ti/TiN structure. The fabrication parameters will be modified to assess their influence in the randomness. To link electrical characteristics to physical and chemical atomic interactions, a complementary approach is required: the simulation of atomistic models. Finally, the statistical analysis will be crucial to guide the design of the operative algorithm for the implementation of PUF aa well as TRNG.

SecuReFET: Secure Circuits through inherent Reconfigurable FE

Project title: Secure Circuits through inherent Reconfigurable FET

Acronym: SecuReFET

Principal Investigators:

Project Staff:

  • Jan Gärtner; process support
  • Thorsten Neuhaus, tool support

Available open position:

  • TBA at Namlab
  • TBA at TU Dresden

Attribution within the Priority Program:

Area 1 “Nano-electronics for Security“

Interdisciplinary Group IG1 “Secret Generation”

Interdisciplinary Group IG3 “Physical Attack Resilience”

Link to Project Website: TBA

Project Abstract: Today’s societies critically depend on electronic systems. Over the last years, the security of these system has been at risk by a number of hardware-level attacks that circumvent software-level security mechanisms.
Solutions based on classical CMOS electronics have been shown to be either cost intensive due to a high area overhead or energy inefficient. One promising option to fight against these hardware level attacks in future electronic system are emerging nanotechnologies, such as reconfigurable field effect transistors (RFETs) with programmable p- and n-function. The runtime-reconfigurable nature of those nano-electronic devices yields to an inherent polymorphic functionality at the logic gate level. As a result circuits made of regular RFET blocks are able to provide a large number of possible functional combinations based on the apparently same circuit representation. The manufacturers, therefore, are able to program the desired functionality after chip production. The big difference to standard CMOS electronics is, that the actual circuit or function remains hidden since they cannot be differentiated from other possible combinations by physical reverse engineering or electrical monitoring of the circuit (i.e., by side-channel attacks).

In SecuReFET, such circuits will be developed exploiting the inherent polymorphic property of RFETs. RFET-based secure circuit cells, which aim to protect proprietary IP designs and provide physically unclonable functions, will be designed, modelled, manufactured and measured. The benefit of those cells regarding their resilience against side-channel attacks and reverse engineering will be demonstrated. In addition, potential security threats stemming from the reconfigurable nature of the technology, such as hardware Trojans, will be investigated. Measures to mitigate those vulnerabilities by circuit as well as device design will be established. Furthermore, an RFET-compatible automated design-synthesis environment (EDA) for logic and physical design of security circuits will be established based on modified modern design rules. Finally, the developed concepts will be verified and benchmarked by means of modern security tests.

OptiSecure: Securing Nano-Circuits against Optical Probing

Project title: Securing Nano-Circuits against Optical Probing

Acronym: OptiSecure

Principal Investigators:

Project Staff:

  • Thilo Krachenfels, TU Berlin
  • Tuba Kiyan, TU Berlin

Available open position:

  • Research assistant, Uni Bremen, TBA
  • Student research assistant, TU Berlin, TBA

Attribution within the Priority Program:

Area 1 “Nano-electronics for Security“:

Interdisciplinary Group IG3 “Physical Attack Resilience”

Link to Project Website: TBA

Project Abstract: Hardware-level attacks pose a serious threat for the integrity and confidentiality of electronic systems. For example, optical probing, which is a relatively new form of attack against integrated circuits, enables the
contactless extraction of secret information and has been successfully applied on several secure systems. Despite the severe implications of this type of passive attack, no relevant countermeasures are being deployed so far.

This project aims at investigating methods that enable the protection of future integrated nano-circuits against optical probing attacks. To this end, a technology model for the exploration of the relation between geometrical characteristics of the integrated devices and its susceptibility to optical probing attacks shall be derived. At the same time, it shall be
investigated how alternative logic styles and design methodologies can contribute as countermeasures against this kind of passive attack. Furthermore, new kinds of similar optical attacks shall be developed and evaluated in terms of their threat potential. Finally, several test structures and their hardened counterparts shall be integrated into a physical circuit and extensively tested.

RAINCOAT: Randomization in Secure Nano-Scale Microarchitectures

Project title: Randomization in Secure Nano-Scale Microarchitectures

Acronym: RAINCOAT

Principal Investigators:

Project Staff:

Jan Thoma; N.N.

Attribution within the Priority Program:

Area 1 “Nano-electronics for Security“

Area 2 “Hardware Security and Cryptography“

Interdisciplinary Group IG2 “Secure Processing”

Link to Project Website: https://www.seceng.ruhr-uni-bochum.de/research/projects/raincoat/

Project Abstract: During the last two years, attacks exploiting the security critical dependencies between hardware and software gained significant popularity. The technical glue between hardware and software – defined by the microarchitectural level -- revealed a variety of security vulnerabilities, such as Spectre, Meltdown, RowHammer, RamBleed or cache attacks such as Flush+Reload. With the present situation we are now facing two challenges: (a) to find countermeasures against such a large variety of microarchitecture attacks that (b) reflect the new features and issues with latest nano technology.

Prevention of side-channels implies the exclusive use of hardware components as well as a fully uniform program behavior which includes the data and control flows. However, those requirements are extremely difficult to achieve by design both on the hardware and software level.

Thus potential leakages of hardware components need to be carefully evaluated and addressed using countermeasures that implement uniformity or masking techniques manually -- therefore we require randomization on the microarchitecture level.

Goal of this project is the development, security analysis and evaluation of a novel randomization-augmented microarchitecture with respect to the technological challenges in nano-scale technology, including the efficient generation, sharing and distribution of randomness.

STAMPS: From Strain to Trust: tAMper aware silicon PufS

Project title: From Strain to Trust: tAMper aware silicon PufS

Acronym: STAMPS

Principal Investigators:

Project Staff:

  • Carl Riehm, TUM
  • Florin Burcea, TUM
  • N.N., FhG AISEC

Available open position:

at FhG Aisec

Attribution within the Priority Program:

Area 1 “Nano-electronics for Security“

Area 2 “Hardware Security and Cryptography“:

Interdisciplinary Group IG1 “Secret Generation”

Project Abstract: The STAMPS project proposes a PUF-based tamper protection mechanism for embedded systems based on a new CMOS sensor to avoid the need for a backup battery. The sensor makes use of changing electrical properties of mesh elements in a CMOS process when opening the package of an IC: First for detecting physical tampering and second for evaluating it as a Physical Unclonable Function (PUF).

nanoEBeam: E Beam Probing for backside attacks against nanoscale silicon

Project title: E Beam Probing for backside attacks against nanoscale silicon

Acronym: nanoEBeam

Principal Investigators:

Project Staff:

TBA

Available open position:

TBA

Attribution within the Priority Program:

Area 1 “Nano-electronics for Security“

Interdisciplinary Group IG3 “Physical Attack Resilience”

Link to Project Website: TBA

Project Abstract: Currently the most successful attacks are performed through optical techniques for IC signal tracking and defect localization, which are strongly challenged by miniaturization of technology nodes below 10nm. They require complex access strategies such as sophisticated chip substrate thinning down to the μm range. In the context of this project, novel physical side channel attack strategies based on electron beams via E-Beam Probing from the chip backside are to be tested on appropriate highly integrated modern circuits. E-Beam probing through the silicon substrate from the chip backside has already been demonstrated for 120nm technologies. In addition, the successful application for fault localization has recently been demonstrated on a 10nm-node FinFET technology. Conduction of fundamental research of this approach as a potential IC attack technique particularly to the  nanotechnology is therefore urgently required. Due to the achievable local resolution in the nanometer range, which is considerably improved compared to existing optical techniques, the risk of novel attack scenarios arise. Within the framework of this project, e-beam-based attack strategies in combination with novel FIB preparation strategies for precise backside access to functional IC structures on modern 10nm chip technologies will be investigated and compared with previously established optical methods. IC attacks with these techniques are currently unknown.

Contact

Ilia Polian
Prof. Dr. rer. nat. habil.

Ilia Polian

University of Stuttgart

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