36. Physics inspired compact modelling of \$\$\backslashhbox \BiFeO\\_3\$\$based memristors
. Sahitya Yarragolla; Nan Du; Torben Hemke; Xianyue Zhao; Ziang Chen; Ilia Polian and Thomas Mussenbrock. Scientific Reports
12, 1 (November 2022), pp. 20490. DOI: https://doi.org/10.1038/s41598-022-24439-4
AbstractWith the advent of the Internet of Things, nanoelectronic devices or memristors have been the subject of significant interest for use as new hardware security primitives. Among the several available memristors, BiFe\$\$\backslashmathrmØ\\_\3\\$\$ (BFO)-based electroforming-free memristors have attracted considerable attention due to their excellent properties, such as long retention time, self-rectification, intrinsic stochasticity, and fast switching. They have been actively investigated for use in physical unclonable function (PUF) key storage modules, artificial synapses in neural networks, nonvolatile resistive switches, and reconfigurable logic applications. In this work, we present a physics-inspired 1D compact model of a BFO memristor to understand its implementation for such applications (mainly PUFs) and perform circuit simulations. The resistive switching based on electric field-driven vacancy migration and intrinsic stochastic behaviour of the BFO memristor are modelled using the cloud-in-a-cell scheme. The experimental current--voltage characteristics of the BFO memristor are successfully reproduced. The response of the BFO memristor to changes in electrical properties, environmental properties (such as temperature) and stress are analyzed and consistant with experimental results.
35. PA-PUF: A Novel Priority Arbiter PUF
. Simranjeet Singh; Srinivasu Bodapati; Sachin Patkar; Rainer Leupers; Anupam Chattopadhyay and Farhad Merchant. In 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)
, 2022, pp. 1–6. DOI: https://doi.org/10.1109/VLSI-SoC54400.2022.9939642
AbstractThis paper proposes a 3-input arbiter-based novel physically unclonable function (PUF) design. Firstly, a 3-input priority arbiter is designed using a simple arbiter, two multiplexers (2:1), and an XOR logic gate. The priority arbiter has an equal probability of 0’s and 1’s at the output, which results in excellent uniformity (49.45%) while retrieving the PUF response. Secondly, a new PUF design based on priority arbiter PUF (PA-PUF) is presented. The PA-PUF design is evaluated for uniqueness, non-linearity, and uniformity against the standard tests. The proposed PA-PUF design is configurable in challenge-response pairs through an arbitrary number of feed-forward priority arbiters introduced to the design. We demonstrate, through extensive experiments, reliability of 100% after performing the error correction techniques and uniqueness of 49.63%. Finally, the design is compared with the literature to evaluate its implementation efficiency, where it is clearly found to be superior compared to the state-of-the-art.
34. A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications
. Elmira Moussavi; Dominik Sisejkovic; Animesh Singh; Daniyar Kizatov; Rainer Leupers; Sven Ingebrandt; Vivek Pachauri and Farhad Merchant. In 2022 IEEE 23rd Latin American Test Symposium (LATS)
, 2022, pp. 1–4. DOI: https://doi.org/10.1109/LATS57337.2022.9937020
AbstractThe ion-sensitive field-effect transistor (ISFET) is an emerging technology that has received much attention in numerous research areas, including biochemistry, medicine, and security applications. However, compared to other types of sensors, the complexity of ISFETs make it more challenging to achieve a sensitive, fast and repeatable response. Therefore, various readout circuits have been developed to improve the performance of ISFETs, especially to eliminate the temperature effect. This paper presents a new approach for a temperature-independent readout circuit that uses the threshold voltage differences of an ISFET-MOSFET pair. The Linear Technology Simulation Program with Integrated Circuit Emphasis (LTspice) is used to analyze the ISFET performance based on the proposed readout circuit characteristics. A macro-model is used to model ISFET behavior, including the first-level Spice model for the MOSFET part and Verilog-A to model the surface potential, reference electrode, and electrolyte of the ISFET to determine the relationships between variables. In this way, the behavior of the ISFET is monitored by the output voltage of the readout circuit based on a change in the electrolyte's hydrogen potential (pH), determined by the simulation. The proposed readout circuit has a temperature coefficient of $11.9ppm/^\circC$ for a temperature range of 0-100°C and pH between 1 and 13. The proposed ISFET readout circuit outperforms other designs in terms of simplicity and not requiring an additional sensor.
33. DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis,. Nishant Gupta; Mohil Desai; Mark Wijtvliet; Shubham Rai and Akash Kumar. In 2022 59th ACM/IEEE Design Automation Conference (DAC) (to appear), 2022, pp. 1–6.
32. On the Sustainability of Lightweight Cryptography Based on PUFs Implemented on NAND Flash Memories Using Programming Disturbances
. Nikolaos Athanasios Anagnostopoulos; Yufan Fan; Muhammad Umair Saleem; Nico Mexis; Florian Frank; Tolga Arul and Stefan Katzenbeisser. (April 2022). DOI: https://doi.org/10.36227/techrxiv.19529263.v1
31. Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques. Sajjad Parvin; Thilo Krachenfels; Shahin Tajik; Jean-Pierre Seifert; Frank Sill Torres and Rolf Drechsler. In To appear in Proceedings of the 27th Asia and South Pacific Design Automation Conference (ASP-DAC’22), 2022.
30. pHGen: A pH-Based Key Generation Mechanism Using ISFETs. Elmira Moussavi; Dominik Sisejkovic; Fabian Brings; Daniyar Kizatov; Animesh Singh; Xuan Thang Vu; Sven Ingebrandt; Rainer Leupers; Vivek Pachauri and Farhad Merchant. In Proceedings of the 2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2022.
29. Write Me and I’ll Tell You Secrets – Write-After-Write Effects On Intel CPUs
. Jan Philipp Thoma and Tim Güneysu. In 25th International Symposium on Research in Attacks, Intrusions and Defenses
, Limassol, Cyprus, 2022, pp. 72–85. DOI: https://doi.org/10.1145/3545948.3545987
AbstractThere is a long history of side channels in the memory hierarchy of modern CPUs. Especially the cache side channel is widely used in the context of transient execution attacks and covert channels. Therefore, many secure cache architectures have been proposed. Most of these architectures aim to make the construction of eviction sets infeasible by randomizing the address-to-cache mapping. In this paper, we investigate the peculiarities of write instructions in recent CPUs. We identify Write+Write, a new side channel on Intel CPUs that leaks whether two addresses contend for the same cache set. We show how Write+Write can be used for rapid construction of eviction sets on current cache architectures. Moreover, we replicate the Write+Write effect in gem5 and demonstrate on the example of ScatterCache 57 how it can be exploited to efficiently attack state-of-the-art cache randomization schemes. In addition to the Write+Write side channel, we show how Write-After-Write effects can be leveraged to efficiently synchronize covert channel communication across CPU cores. This yields the potential for much more stealthy covert channel communication than before.
28. Stochastic behavior of an interface-based memristive device
. Sahitya Yarragolla; Torben Hemke; Jan Trieschmann; Finn Zahari; Hermann Kohlstedt and Thomas Mussenbrock. Journal of Applied Physics
131, 13 (2022), pp. 134304. DOI: https://doi.org/10.1063/5.0084085
27. Study on sneak path effect in self-rectifying crossbar arrays based on emerging memristive devices
. Ziang Chen; Guofu Zhang; Hao Cai; Christopher Bengel; Feng Liu; Xianyue Zhao; Shahar Kvatinsky; Heidemarie Schmidt; Rainer Waser; Stephan Menzel and Nan Du. Frontiers in Electronic Materials
2, (2022). DOI: https://doi.org/10.3389/femat.2022.988785
AbstractThe high demand for performance and energy efficiency poses significant challenges for computing systems in recent years. The memristor-based crossbar array architecture is enthusiastically regarded as a potential competitor to traditional solutions due to its low power consumption and fast switching speed. Especially by leveraging self-rectifying memristive devices, passive crossbar arrays potentially enable high memory densities. Nonetheless, due to the lack of a switching control per cell, these passive, self-rectifying memristive crossbar arrays (srMCA) suffer from sneak path current issues that limit the range of accurate operation of the crossbar array. In this work, the sneak path current issues in the passive srMCAs based on self-rectifying bipolar and complementary switching memristive devices are comparatively analyzed. Under consideration of the worst-case scenario, three reading schemes are investigated: one wordline pull-up (OneWLPU), all wordline pull-up (AllWLPU), and floating (FL) reading schemes. As a conclusion, despite different switching dynamics, both types of self-rectifying memristive devices can efficiently suppress sneak path current in the srMCAs. In the FL reading scheme, the sneak path current flowing through the unselected reversely biased memristive cells in the srMCA can be considered as an accurate estimation for the practical sneak path current in the srMCA. By analyzing the sneak path current in the srMCAs with a size up to 64 × 64, it is demonstrated that the leakage current plays a crucial role for suppressing the sneak path current, and the sneak path current via an individual cell exhibits a continuous decrease while the accumulated total sneak path current in the unselected reverse biased region is increasing with expanding the crossbar size. The comparative study on the bipolar and complementary memristive devices based srMCAs under diverse reading schemes reveals the influence of the switching dynamics on the sneak path current effect in the srMCAs, and provides a beneficial reference and feasible solutions for the future optimization of the crossbar topology with the intention of mitigating sneak path effects.
26. Review on data-centric brain-inspired computing paradigms exploiting emerging memory devices
. Wei Wang; Shahar Kvatinsky; Heidemarie Schmidt and Nan Du. Frontiers in Electronic Materials
2, (2022). DOI: https://doi.org/10.3389/femat.2022.1020076
AbstractBiologically-inspired neuromorphic computing paradigms are computational platforms that imitate synaptic and neuronal activities in the human brain to process big data flows in an efficient and cognitive manner. In the past decades, neuromorphic computing has been widely investigated in various application fields such as language translation, image recognition, modeling of phase, and speech recognition, especially in neural networks (NNs) by utilizing emerging nanotechnologies; due to their inherent miniaturization with low power cost, they can alleviate the technical barriers of neuromorphic computing by exploiting traditional silicon technology in practical applications. In this work, we review recent advances in the development of brain-inspired computing (BIC) systems with respect to the perspective of a system designer, from the device technology level and circuit level up to the architecture and system levels. In particular, we sort out the NN architecture determined by the data structures centered on big data flows in application scenarios. Finally, the interactions between the system level with the architecture level and circuit/device level are discussed. Consequently, this review can serve the future development and opportunities of the BIC system design.
25. Robust Reconfigurable Field Effect Transistors Process Route Enabling Multi-VT Devices Fabrication for Hardware Security Applications
. Giulio Galderisi; Thomas Mikolajick and Jens Trommer. In 2022 Device Research Conference (DRC)
, 2022, pp. 1–2. DOI: https://doi.org/10.1109/DRC55272.2022.9855805
24. Reconfigurable Field Effect Transistors Design Solutions for Delay-Invariant Logic Gates
. Giulio Galderisi; Thomas Mikolajick and Jens Trommer. IEEE Embedded Systems Letters
14, 2 (2022), pp. 107–110. DOI: https://doi.org/10.1109/LES.2022.3144010
23. Reconfigurable field effect transistors: A technology enablers perspective
. T. Mikolajick; G. Galderisi; S. Rai; M. Simon; R. Böckle; M. Sistani; C. Cakirlar; N. Bhattacharjee; T. Mauersberger; A. Heinzig; A. Kumar; W.M. Weber and J. Trommer. Solid-State Electronics
194, (2022), pp. 108381. DOI: https://doi.org/10.1016/j.sse.2022.108381
AbstractWith classical scaling of CMOS transistors according to Dennard’s scaling rules running out of steam, new possibilities to increase the functionality of an integrated circuit at a given footprint are becoming more and more desirable. Among these approaches the possibility to reconfigure the functionality of a transistor on the single devices level stand out, as by such an approach the same physical circuitry is enabled to perform different tasks in different configurations of the circuit. Reconfigurable transistors that allow the reconfiguration from a p-channel to an n-channel transistor and vice versa have emerged as an important example of such devices. The basic concepts required to built such devices have been proposed more then 20 years ago and the field has continuously developed ever since. In this article first the basic classification of reconfigurable field effect transistors is reviewed an described form a new angle. In the second part the important technology enablers to construct reconfigure field effect transistors are examined. Further the historical development, starting at the proposal of the main concepts up to the current status of device and circuit development are described. The most important additional features that have been introduced in the last years in order to even further increase the flexibility of the devices are discussed. Finally the application potential of reconfigurable transistors is described placing the spotlight on hardware security and neuromorphic applications.
22. The IC Ultra-Thin Back Surface - A Field of Real Nanoscale Fault Isolation Opportunities Requiring a Skillful Sample Preparation
. C. Boit; J. Jatzkowski; F. Altmann; M. DiBattista; S. Silverman; G. Zwicker; N. Herfurth; E. Amini and J.-P. Seifert. In 2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
, 2022, pp. 1–6. DOI: https://doi.org/10.1109/IPFA55383.2022.9915783
21. Second Harmonic Generation Exploiting Ultra-Stable Resistive Switching Devices for Secure Hardware Systems
. Ziang Chen; Nan Du; Mahdi Kiani; Xianyue Zhao; Ilona Skorupa; Stefan E. Schulz; Danilo Bürger; Massimiliano Di Ventra; Ilia Polian and Heidemarie Schmidt. IEEE Transactions on Nanotechnology
21, (2022), pp. 71–80. DOI: https://doi.org/10.1109/TNANO.2021.3135713
AbstractNeural network (NN) algorithms have become the dominant tool in visual object recognition, natural language processing, and robotics. To enhance the computational efficiency of these algorithms, in comparison to the traditional von Neuman computing architectures, researchers have been focusing on memristor computing systems. A major drawback when using memristor computing systems today is that, in the artificial intelligence (AI) era, well-trained NN models are intellectual property and, when loaded in the memristor computing systems, face theft threats, especially when running in edge devices. An adversary may steal the well-trained NN models through advanced attacks such as learning attacks and side-channel analysis. In this paper, we review different security techniques for protecting memristor computing systems. Two threat models are described based on their assumptions regarding the adversary’s capabilities: a black-box (BB) model and a white-box (WB) model. We categorize the existing security techniques into five classes in the context of these threat models: thwarting learning attacks (BB), thwarting side-channel attacks (BB), NN model encryption (WB), NN weight transformation (WB), and fingerprint embedding (WB). We also present a cross-comparison of the limitations of the security techniques. This paper could serve as an aid when designing secure memristor computing systems.
19. Towards a Formally Verified Hardware Root-of-Trust for Data-Oblivious Computing. L. Deutschmann; J. Müller; M. R. Fadiheh; D. Stoffel and W. Kunz. In to appear in Procceedings of IEEE/ACM Design Automation Conference (DAC), 2022, 2022.
18. An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors
. Mohammad Rahmani Fadiheh; Alex Wezel; Johannes Muller; Jorg Bormann; Sayak Ray; Jason M. Fung; Subhasish Mitra; Dominik Stoffel and Wolfgang Kunz. IEEE Transactions on Computers
(2022), pp. 1–1. DOI: https://doi.org/10.1109/TC.2022.3152666
17. On the Sustainability of Lightweight Cryptography Based on PUFs Implemented on NAND Flash Memories Using Programming Disturbances
. Nikolaos Athanasios Anagnostopoulos; Yufan Fan; Muhammad Umair Saleem; Nico Mexis; Florian Frank; Tolga Arul and Stefan Katzenbeisser. 2022.2022. DOI: https://doi.org/10.48550/ARXIV.2204.02498
16. A scalable & comprehensive resilience concept against optical & physical IC backside attacks
. Norbert Herfurth; Elham Amini; Marco Lisker; Jean-Pierre Seifert and Christian Boit. In 2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
, 2022, pp. 1–6. DOI: https://doi.org/10.1109/IPFA55383.2022.9915714
15. Risky Translations: Securing TLBs against Timing Side Channels. Florian Stolz; Jan Philipp Thoma; Pascal Sasdrich and Tim Güneysu. 2022.2022.
14. Realization of Memristor-aided Logic Gates with Analog Memristive Devices
. Hao Cai; Ziang Chen; Xianyue Zhao; Christopher Bengel; Feng Liu; Heidemarie Schmidt; Stephan Menzel and Nan Du. In 2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)
, 2022, pp. 1–4. DOI: https://doi.org/10.1109/MOCAST54814.2022.9837637
13. Redox Memristors with Volatile Threshold Switching Behavior for Neuromorphic Computing
. Yu Hao Wang; Tian Cheng Gong; Ya Xin Ding; Yang Li; Wei Wang; Zi Ang Chen; Nan Du; Erika Covi; Matteo Farronato; Dniele Ielmini; Xu Meng Zhang and Qing Luo. 20, 4 (2022), pp. 356--374. DOI: https://doi.org/10.1016/j.jnlest.2022.100177
AbstractThe spiking neural network (SNN), closely inspired by the human brain, is one of the most powerful platforms to enable highly efficient, low cost, and robust neuromorphic computations in hardware using traditional or emerging electron devices within an integrated system. In the hardware implementation, the building of artificial spiking neurons is fundamental for constructing the whole system. However, with the slowing down of Moore’s Law, the traditional complementary metal-oxide-semiconductor (CMOS) technology is gradually fading and is unable to meet the growing needs of neuromorphic computing. Besides, the existing artificial neuron circuits are complex owing to the limited bio-plausibility of CMOS devices. Memristors with volatile threshold switching (TS) behaviors and rich dynamics are promising candidates to emulate the biological spiking neurons beyond the CMOS technology and build high-efficient neuromorphic systems. Herein, the state-of-the-art about the fundamental knowledge of SNNs is reviewed. Moreover, we review the implementation of TS memristor-based neurons and their systems, and point out the challenges that should be further considered from devices to circuits in the system demonstrations. We hope that this review could provide clues and be helpful for the future development of neuromorphic computing with memristors.