4th Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec’26)

20 – 22 April 2026, Verona , Italy, co-located with Design Automation and Test in Europe (DATE) Conference

Download of Workshop Materials

Workshop speakers were free to provide materials (slides or papers) for publications. The provided materials are available from the list below.

4th Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec’26)

20  – 22 April 2026, Verona, Italy, co-located with Design Automation and Test in Europe (DATE) Conference

We regret to inform that our foreseen keynote speaker Professor Massimo Alioto was forced to cancel his participation due to health reasons. We are wishing Professor Alioto swift recovery.

We are pleased to announce that Professor Francesco Regazzoni, University of Amsterdam and USI Lugano, has kindly agreed to join us as keynote speaker. We are grateful for Francesco’s willingness to step in and look forward to his keynote entitled “(Re-)Thinking Hardware Security in the Nanoscale Age”.

Workshop Scope

Today’s societies critically depend on electronic systems. Security of such systems are facing completely new challenges due to the ongoing transition to radically new types of nano-electronic devices, such as memristors, spintronics, or carbon nanotubes. The use of such emerging nano-technologies is inevitable to address the essential needs related to energy efficiency, computing power and performance. Therefore, the entire industry are switching to emerging nano-electronics alongside scaled CMOS technologies in heterogeneous integrated systems. These technologies come with new properties and also facilitate the development of radically different computer architectures.

The fourth edition of the NanoSec workshop will bring together researchers from hardware-oriented security and from emerging hardware technology. It will explore the potential of new technologies and architectures to provide new opportunities for achieving security targets, but it will also raise questions about their vulnerabilities to new types of hardware-oriented attacks. The workshop is based on a Priority Program https://spp-nanosecurity.uni-stuttgart.de/ funded since 2019 by the German DFG, and will be open to members and non-members of that Priority Program alike.

Technical Program

Session chair: Ilia Polian (University of Stuttgart)

(Re-)Thinking Hardware Security in the Nanoscale Age
Francesco Regazzoni, University of Amsterdam and USI Lugano

Abstract

Session chair: Nan Du, IPHT Jena and University of Jena

Integrating Optical Probing Security Evaluation Framework Into ASIC Design Flow
Sajjad Parvin (U Bremen), Frank Sill Torres (DLR), Rolf Drechsler (U Bremen an DFKI)

Limitations of Architectural Simulation for Security: Why Transient-Execution Countermeasures Must Be Designed and Evaluated on the RTL
Tobias Jauch, Philipp Schmitz, Alex Wezel, Simón Blanko Ortiz, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz (RPTU Kaiserslautern-Landau)

Modeling of Tamper Resistance to Correlative Electromagnetic Analysis for Voltage-scaled Circuits
Yusuke Matsubayashi, Kazuki Minamiguchi, Hiroki Nishikawa, Yoshihiro Midoh, Noriyuki Miura and Jun Shiomi (U Osaka)

Abstract

EMBOSOM: Embedded Software Security into Modern Emerging Hardware Paradigms
Rolf Drechsler (U Bremen), Tim Güneysu and Pascal Sasdrich (RU Bochum), Christoph Lüth (U Bremen)

HaSPro: Verifiable Hardware Security for Out-of-Order Processors
Thomas Eisenbarth (U Lübeck), Wolfgang Kunz (TU Kaiserslautern)

MemCrypto: Towards Secure Electroforming-free Memristive Cryptographic Implementations
Nan Du (FSU Jena), Ilia Polian (U Stuttgart)

NanoSec2: Nanomaterial-based platform electronics for PUF circuits with extended entropy sources
Sascha Herrmann (TU Chemnitz), Stefan Katzenbeisser (U Passau), Elif Kavun (U Passau)

OnE-Secure: Securing State-of-the-Art Chips Against High-Resolution Contactless Optical and Electron-Beam Probing Attacks
Sebastian Brand (FhG IMWS), Rolf Drechsler (U Bremen), Jean-Pierre Seifert TU Berlin), Frank Sill Torres (DLR)

RAINCOAT: Randomization in Secure Nano-Scale Microarchitectures 2
Lucas Davi (U Duisburg-Essen), Tim Güneysu (RU Bochum)

SecuReFET: Secure Circuits through Inherent Reconfigurable FET
Akash Kumar (TU Dresden), Thomas Mikolajick (NaMLab GmbH)

SeMSiNN: Secure Mixed-SIgnal Neural Networks
Maurits Ortmanns (U Ulm), Ilia Polian (U Stuttgart)

SSIMA: Scalable Side-Channel Immune Micro-Architecture
Amir Moradi (TU Darmstadt)

STAMPS-PLUS: Exploration of an integrated Strain-based TAMPer Sensor for Puf and trng concepts with best-in-class Leakage resilience and robUStness
Ralf Brederlow (TU Munich), Matthias Hiller (FhG AISEC), Michael Pehl (TU Munich)

Session chair: Mahdi Fazeli, Halmstad University

Security Aspects of Computing-in-Memory Architectures in AI Era
Ahmad Patooghy (North Caroline A&T U), Mahdi Fazeli (Halmstad University)

A Case Study: Secure Reconfigurable FET-Based SRAM Architecture for In-Memory Computing
Farah Naz Syed (RU Bochum), Peng Chong, Juan Martinez, Stefan Slesazeck, Jens Trommer, Thomas Mikolajick (NamLab gGmbH), Akash Kumar (RU Bochum)

Abstract

Session chair: Francesco Regazzoni, University of Amsterdam and USI Lugano

Preventing Distinguishability between Multiplication and Squaring Operations
Alkistis Aikaterini Sigourou (IHP), Zoya Dyka (IHP and BTU Cottbus-Senftenberg), Peter Langendoerfer (BTU Cottbus-Senftenberg), Ievgen Kabin (IHP)

Logic Locking with Lightweight Cryptography
Levent Aksoy (TU Tallinn), Muhammad Sohaib Munir (TU Tallinn), Sedat Akleylek (U Tartu)

Lifecycle Protecting Integrated Circuits Using Physical Unclonable Functions
Michael Pehl, Carl Riehm, Tim Music (TU Munich), Valentin Huber, Matthias Hiller (FhG AISEC), Ralf Brederlow (TU Munich)

Abstract

Session chair: Paolo Palmieri, University College Cork

Exploiting Ultra-Low Voltage RFETs for Dynamic Circuit Obfuscation in Embedded Security
Giulio Galderisi, Yuxuan He (NaMLab gGmbH), Aniruddh Holemadlu (RU Bochum), Juan Martinez, Thomas Mikolajick (NaMLab gGmbH), Akash Kumar (RU Bochum), Jens Trommer NaMLab gGmbH

Dynamic Key Change Scheme for Protecting Arbitrary Data Communication in a Multi-Die IC
Zheng-Hao Wang, Shi-Yu Huang (NTHU Taiwan), Chi-Kang Chen (TESDA)

Evaluation of Carbon Nanotube-based Integrated Crossbar PUFs
Martin Schmid (U Passau), Simon Böttger, Martin Ernst, Martin Hartmann, Sascha Hermann (TU Chemnitz), Elif Bilge Kavun (TU Dresden) Stefan Katzenbeisser (U Passau)

Abstract

Call for Papers

The workshop invites submissions on, but not limited to, the following topics:

  • Nano-electronic security primitives, such as physical unclonable functions, random number generators, cryptographic blocks, reconfigurable nano-fabrics, or obfuscation/camouflaging structures
  • Integration of secure primitives into larger systems, protocols and architectures, translating security guarantees defined and validated for lower-level primitives in higher-order, system- and architecture-level security properties
  • Attacks against systems with nano-electronic components, including side-channel analysis, fault injection, microarchitectural covert channels, and countermeasures against such attacks

This year, the workshop will feature a Special Session on Secure Compute-in-Memory Architectures, organized by Prof. Mahdi Fazeli  (Halmstad University) and Prof. Ahmad Patooghy (North Caroline A&T University)

A submission can describe a novel scientific result, provide a position statement about a new and relevant problem, or report a case study on practical experiences with a technique from the list above. The submissions should not be formally published in the past. The workshop will have no formal proceedings, so authors will be free to resubmit their work to conferences or journals. Accepted papers can, at the discretion and with an approval of their authors, be published on the workshop’s website. You will be able to indicate during submission whether you are submitting to the regular program or to the Special Session on Secure Compute-in-Memory Architectures.

Call for Papers

Author instructions:

Submissions in form of full 6-page papers or 1-2 page extended abstracts (in IEEE double-column format, either A4 or US Letter) should be submitted through EasyChair:

EasyChair

Key dates:

Submission deadline: February 2, 2026
Acceptance notification: February 16, 2026

PDF file for publishing on the workshop’s website (optional): March 10, 2026

Workshop: April 20 – 22, 2026 (exact day and time slot to be announced soon)

Registration:
This workshop is co-located with the Design, Automation and Test in Europe Conference and will use its registration facilities. Please register through the DATE website:

Date Website

Workshop organizers:

Ilia Polian, University of Stuttgart, Germany
Nan Du, Friedrich Schiller University Jena, Germany
Yunsi Fey, Northeaster University, Boston, USA
Shahar Kvatinsky, Technion – Israel Institute of Technology
Fareena Saqib, University of North Carolina, Charlotte, USA

The workshop is organized by the Priority Program Nano Security
https://spp-nanosecurity.uni-stuttgart.de/

Contact

This image showsIlia Polian

Ilia Polian

Prof. Dr. rer. nat. habil.

University of Stuttgart

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