3rd Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec’25)
29 March – 2 April 2025, Lyon, France, co-located with Design Automation and Test in Europe (DATE) Conference
Workshop Scope
Today’s societies critically depend on electronic systems. Security of such systems are facing completely new challenges due to the ongoing transition to radically new types of nano-electronic devices, such as memristors, spintronics, or carbon nanotubes. The use of such emerging nano-technologies is inevitable to address the essential needs related to energy efficiency, computing power and performance. Therefore, the entire industry are switching to emerging nano-electronics alongside scaled CMOS technologies in heterogeneous integrated systems. These technologies come with new properties and also facilitate the development of radically different computer architectures.
The third edition of the NanoSec workshop will bring together researchers from hardware-oriented security and from emerging hardware technology. It will explore the potential of new technologies and architectures to provide new opportunities for achieving security targets, but it will also raise questions about their vulnerabilities to new types of hardware-oriented attacks. The workshop is based on a Priority Program https://spp-nanosecurity.uni-stuttgart.de/ funded since 2019 by the German DFG, and will be open to members and non-members of that Priority Program alike.
Technical Program
Session chair: Ilia Polian, University of Stuttgart
MemComputing and Implications for Security
Massimiliano Di Ventra, University of California San Diego
Session chair: Session chair: TBD
An Obfuscated 2-bit Adder/Half-Subtract Circuit with Reconfigurable Field Effect Transistors
Giulio Galderisi1, Niladri Bhattacharjee1, Marc Wijvliet2, Shubham Rai2, Akash Kumar3, Thomas Mikolajick1,4, Jens Trommer1,
1NaMLab GmbH, Dresden, Germany, 2Chair of Processor Design, TU Dresden, Germany, 3Chair of Embedded Systems, Ruhr University Bochum, Germany, 4Chair of Nanoelectronics, TU Dresden, Germany
Designing Memory Protection for a RISC-V Nano-VP
Spandan Das, Christoph Lüth, Rolf Drechsler
Dept. Mathematics and Informatics, University of Bremen, Bremen, Germany
In-and-Beyond Boundaries: GPIO Signaling Research and Use-Cases with TrustZone
Christian Niesler1, Markus Ströhnisch1, Moritz Peters2, Tim Güneysu2, Lucas Davi1,
1University of Duisburg-Essen, Essen, Germany, 2Ruhr University Bochum, Germany
Session chair: Session chair: TBD
Distinguishability between Multiplication and Squaring Operations: a New Marker
Alkistis Aikaterini Sigourou1, Zoya Dyka1,2, Peter Langendoerfer1,2, Ievgen Kabin1,
1IHP – Leibniz-Institut für innovative Mikroelektronik, Frankfurt (Oder), Germany, 2BTU Cottbus-Senftenberg, Cottbus, Germany
SCA Test Results Depend on the Measurement Equipment: Riscure vs. Teledyne LeCroy
Dmytro Petryk1, Zoya Dyka1,2, Peter Langendoerfer1,2, Ievgen Kabin1,
1IHP – Leibniz-Institut für innovative Mikroelektronik, Frankfurt (Oder), Germany, 2BTU Cottbus-Senftenberg, Cottbus, Germany
OnE-Secure: Securing State-of-the-Art Chips Against High-Resolution Contactless Optical and Electron-Beam Probing Attacks
Sebastian Brand (FhG IMWS), Rolf Drechsler (U Bremen), Jean-Pierre Seifert TU Berlin), Frank Sill Torres (DLR)
STAMPS-PLUS: Exploration of an integrated Strain-based TAMPer Sensor for Puf and trng concepts with best-in-class Leakage resilience and robUStness
Ralf Brederlow (TU Munich), Matthias Hiller (FhG AISEC), Michael Pehl (TU Munich)
RAINCOAT: Randomization in Secure Nano-Scale Microarchitectures 2
Lucas Davi (U Duisburg-Essen), Tim Güneysu (RU Bochum)
EMBOSOM: Embedded Software Security into Modern Emerging Hardware Paradigms
Rolf Drechsler (U Bremen), Tim Güneysu (RU Bochum), Pascal Sasdrich (RU Bochum), Christoph Lüth (U Bremen)
MemCrypto: Towards Secure Electroforming-free Memristive Cryptographic Implementations
Nan Du (FSU Jena), Ilia Polian (U Stuttgart)
HaSPro: Verifiable Hardware Security for Out-of-Order Processors
Thomas Eisenbarth (U Lübeck), Wolfgang Kunz (TU Kaiserslautern)
NanoSec2: Nanomaterial-based platform electronics for PUF circuits with extended entropy sources
Sascha Herrmann (TU Chemnitz), Stefan Katzenbeisser (U Passau), Elif Kavun (U Passau)
SecuReFET: Secure Circuits through Inherent Reconfigurable FET
Akash Kumar (TU Dresden), Thomas Mikolajick (NaMLab GmbH)
SSIMA: Scalable Side-Channel Immune Micro-Architecture
Amir Moradi (TU Darmstadt)
SeMSiNN: Secure Mixed-SIgnal Neural Networks
Maurits Ortmanns (U Ulm), Ilia Polian (U Stuttgart)
April 2, 2025
Call for Papers
The workshop invites submissions on, but not limited to, the following topics:
- Nano-electronic security primitives, such as physical unclonable functions, random number generators, cryptographic blocks, reconfigurable nano-fabrics, or obfuscation/camouflaging structures
- Integration of secure primitives into larger systems, protocols and architectures, translating security guarantees defined and validated for lower-level primitives in higher-order, system- and architecture-level security properties
- Attacks against systems with nano-electronic components, including side-channel analysis, fault injection, microarchitectural covert channels, and countermeasures against such attacks
A submission can describe a novel scientific result, provide a position statement about a new and relevant problem, or report a case study on practical experiences with a technique from the list above. The submissions should not be formally published in the past. The workshop will have no formal proceedings, so authors will be free to resubmit their work to conferences or journals. Accepted papers can, at the discretion and with an approval of their authors, be published on the workshop’s website.
Author instructions:
Submissions in form of full 6-page papers or 1-2 page extended abstracts (in IEEE double-column format, either A4 or US Letter) should be submitted through EasyChair:
Key dates:
Submission deadline: January 14, 2025
Acceptance notification: January 21, 2025
PDF file for publishing on the workshop’s website (optional): March 10, 2025
Workshop: March 31 –April 2, 2025 (exact time slot to be announced)
Registration:
This workshop is co-located with the Design, Automation and Test in Europe Conference and will use its registration facilities. Please register through the DATE website:
Workshop organizers:
Ilia Polian, University of Stuttgart, Germany
Nan Du, Friedrich Schiller University Jena, Germany
Yunsi Fey, Northeaster University, Boston, USA
Shahar Kvatinsky, Technion – Israel Institute of Technology
Fareena Saqib, University of North Carolina, Charlotte, USA
The workshop is organized by the Priority Program Nano Security
https://spp-nanosecurity.uni-stuttgart.de/
Contact
Ilia Polian
Prof. Dr. rer. nat. habil.University of Stuttgart